Design tools for improved hardware security of RFETs

What should a computer chip do? What architecture should it have and what components should it contain? What should the circuit diagram look like, where should connections and transistors be placed? Such questions are answered in chip design. Suitable design tools and libraries are crucial for the realization of application-specific integrated circuits with high performance, reliability and hardware security.

In the "DI-ReDesign" project, GLOBALFOUNDRIES LLC & Co. KG (Dresden), NaMLab GmbH (Dresden), Ruhr University Bochum, the University of Bremen, Technische Universität Berlin, Universities of Applied Sciences TH Mittelhessen (Gießen) and Fraunhofer IMWS are working together to develop open-source design tools and libraries specifically tailored to reconfigurable field effect transistors (RFETs). "These novel semiconductor devices enable higher integration density, improved energy efficiency and faster switching speeds. RFETs also offer considerable advantages in terms of cyber security, temperature stability and signal quality, which makes them interesting for a wide range of applications," says Frank Altmann, head of the " Electronic Materials and Components " business unit, who is coordinating the project at the Fraunhofer IMWS.

The unique properties of RFETs allow versatile applications in digital and analog circuits, for example for signal processing, neural networks and low-temperature electronics. In order to implement complex, highly innovative circuit designs, an open design library and an automated design environment (Electronic Design Automation, EDA) are to be created. The project partners want to use this to provide an open source development environment for innovative electronic solutions based on RFETs. The library contains core properties of the cells for logical and physical synthesis without disclosing information about the exact process or the underlying component physics.

"Partners from industry can then very quickly build on the new design tools, adapt and expand them. This facilitates access to RFET technology and also improves chip design in terms of hardware security," says Altmann. The project results will also give designers and end customers the opportunity to incorporate resistance to possible attack scenarios into the development of their products at an early stage.

The activities of the Fraunhofer IMWS in the project are primarily aimed at testing the resilience of the circuits to reverse engineering and manipulation. Potential attackers use special side-channel methods to try to find out the logical interconnections of the chip structures or electrical signal sequences, read out or influence switching processes and memory contents. This enables counterfeiting, manipulation of chip functionality or misuse of sensitive information. The circuit blocks designed in "DI-ReDesign" are therefore comprehensively evaluated for their security against hardware attacks. Detected vulnerabilities can then be directly taken into account by an adapted chip design.

The Fraunhofer IMWS uses high-resolution electron microscopic scanning methods, known as e-beam probing, to test potential attack scenarios. "For example, we can directly visualize the circuitry of the RFETs using scanning electron microscopy contrast mechanisms and even influence it by interacting with the electron beam. We are also further developing preparation techniques that we have already tested in order to evaluate the feasibility and efficiency of large-area access to transistor structures," says Altmann. New methods for signal tracking are also being used and their potential for hardware attacks is being tested.