Quality and reliability for hybrid bonding through powerful analysis methods

Semiconductor wafers are the central raw material for microelectronics manufacturing processes. The individual chips containing the integrated circuits (ICs) required for the function are processed on these thin discs, usually made of silicon. To connect chips electrically either directly to each other or via a common carrier substrate, contacting techniques using, for example, extremely fine bonding wires or miniaturized solder contacts have been used to date. The mechanical 3D assembly of stacked chips or the attachment of the individual ICs to a substrate is usually supported by adhesive technologies.

For special applications, such as the manufacture of micromechanical sensors in microsystems technology, alternative bonding methods for stacking wafers and chips have been developed in the past.  The "direct wafer bonding" process, for example, is based on the spontaneous formation of chemical bonds at the common interface, supported by thermal treatments, when two pure and flat wafer surfaces are brought into contact with each other. Until now, however, this method has only been used for the purely mechanical assembly of such components or for the production of large-area layer substrates, but not for the purpose of electrical contacting.

As a new, highly innovative technology, "hybrid bonding" now combines the two functions of mechanical connection formation and electrical contacting between the many individual connection surfaces of the chips. On a laboratory scale, the process already enables the manufacture and mutual electrical connection of IC contact surfaces with dimensions of approximately half a micrometer in length and distance. This means that one million individual electrical contact points can be created on one square millimeter of chip surface and electrically connected to a second chip applied vertically "face-to-face." This high contact density, as well as the shortened signal paths between the respective opposite areas of both chips, enable both the simultaneous parallel transmission of many individual electronic signals and very high signal transmission speeds for the electronic interaction of different semiconductor components.

These capabilities are fundamental prerequisites for key future concepts in microelectronics based on the 3D integration of components and, in particular, chiplet architecture. This concept involves dividing increasingly complex and larger individual chips into smaller, partially functional semiconductor components known as chiplets. At the system level, the division of complex "system-on-chip" components into smaller chiplets can result in significantly faster development times, more cost-effective manufacturing processes, more flexible supply chains, and easier adaptation to the requirements of different customers. This takes into account the high development pressure in the market, which is driven by the extreme computing power requirements of artificial intelligence applications as well as automotive applications, e.g., for highly automated or autonomous driving.

However, the use of the chiplet concept requires that the interaction of separate chiplet semiconductor components achieves a level of performance in terms of signal density and signal speed that is comparable to the monolithic components used to date. The high electrical connection densities required for this cannot be achieved with existing solder contact technologies and can only be realized using hybrid bonding processes. In addition to very powerful complex microelectronic systems, memory devices and semiconductor image sensors also benefit from the new technology. Overall, hybrid bonding is therefore a key technology within current developments in microelectronics.

Technically, the wafer or chip surfaces consist of a layer of an electrically non-conductive, mostly silicate dielectric that insulates the embedded miniaturized electrical contact surfaces made of copper from each other. In the first step, hybrid bonding requires a specialized polishing process that ensures high quality in terms of flatness and minimal roughness of the dielectric surface.  During polishing, however, the individual copper surfaces must also be deliberately abraded slightly more so that their level is ultimately a few nanometers below the dielectric surface. This step is followed by complex chemical cleaning and pretreatment processes of the surface, including plasma processing to activate the dielectric. The wafers or chips are then positioned on top of each other with very high precision and brought into contact.

Subsequently, two separate bonding processes take place in succession in the common bonding area. First, supported by various temperature processes, only the dielectric contact areas of the two components are bonded by direct wafer bonding, without contacting the copper surfaces. This ensures the mechanical stability and electrical insulation of the connections that are still to be formed. In the second step, further treatment is carried out at a higher temperature. As a result of thermal expansion, mutual mechanical contacting of the copper areas is now also achieved, and a stable metallic and electrically conductive connection is formed by subsequent temperature-assisted diffusion processes. As a result, the complex contact and conductor systems of the two chips positioned on top of each other are interconnected by hundreds of thousands to millions of individual contacts.

“Wafer bonding processes have been commonly used for semiconductor components that serve as sensors in automobiles, for example, for airbags, ABS, ESP, or engine control in the powertrain. Hybrid bonding has taken this connection technology to a whole new level. It is now a very important building block for enabling the most innovative integration concepts at the global forefront of microelectronics, such as highly compact silicon components made from variably integrable chiplets. Issues relating to process evaluation and quality and reliability assurance, in which we already have many years of extensive expertise, are thus also becoming even more important," says Falk Naumann, who is supervising the project at Fraunhofer IMWS, which will run until January 2028.

In hybrid bonding, the electrical and mechanical connection is not created by an intermediate layer (as in soldering), but by direct atomic interaction between the contact surfaces. This makes it all the more important to verify their quality and suitability for the process. It is equally important to be able to identify and clarify possible defect formations and interactions of the wafer surfaces with subsequent processes and thus prevent them in a timely manner. The surface and material properties of the wafers, which determine the contact behavior, therefore play a decisive role.

This is because both the dielectric materials and the copper contacts undergo changes during pre-treatment as well as during the actual bonding process. "With our technical equipment and prior knowledge, we are ideally placed to understand the mutual interaction between the material surface and plasma activation, as well as the reactions that occur during bonding at the interface. This enables us to make recommendations, for example, on which materials are particularly suitable as dielectrics and how plasma processes should be designed in order to achieve good results," says Naumann. "The development of novel dielectrics that can be deposited specifically on wafer surfaces and at the same time meet the high requirements for the insulation properties of the many neighboring contacts and for mechanical stability is a fundamental step in the further development of hybrid bonding. The material reactions that occur during the electrical contact formation of the metallic copper surfaces must also be mastered and understood in detail. We can provide support in this area."

State-of-the-art surface analysis methods such as time-of-flight secondary ion mass spectrometry (ToF-SIMS) and X-ray photoelectron spectroscopy (XPS) are used. In order to correlate the results with the final outcome of the bonding process (such as defects that have arisen or the actual atomic bond strength produced at the wafer and chip level), the microstructural properties of the bonded interface are examined using, for example, scanning transmission electron microscopy (STEM), energy dispersive X-ray spectroscopy (EDX), and electron energy loss spectroscopy (EELS). Methods of high-resolution scanning acoustic microscopy (SAM) are being further developed for defect localization. The project also aims to further develop expertise in high-precision preparation methods using metallography, laser and (focused) ion beam techniques, as well as methods for strength analysis using specialized tests and fracture mechanics modeling.

“The new fields of application for hybrid bonding pose major challenges for the analysis and evaluation procedures required in process development and quality assurance. We can initiate the necessary analysis, measurement, and testing procedures to characterize, understand, and optimize materials, manufacturing processes, and their interactions. By establishing an innovative, combined material diagnostics platform, we are able to comprehensively support the highly complex technological developments in the field of hybrid bonding through microstructure diagnostics, process evaluation, and failure analysis. In this way, we are making a very important contribution to new high-performance applications in cooperation with leading international research partners and companies, and strengthening our role in what is undoubtedly a key future topic in microelectronics," says Naumann.

(October 27, 2025)